diff --git a/arch/powerpc/lib/cache.c b/arch/powerpc/lib/cache.c
index 3e487f5..1916251 100644
--- a/arch/powerpc/lib/cache.c
+++ b/arch/powerpc/lib/cache.c
@@ -9,9 +9,20 @@
 #include <asm/cache.h>
 #include <watchdog.h>
 
+static ulong maybe_watchdog_reset(ulong flushed)
+{
+	flushed += CONFIG_SYS_CACHELINE_SIZE;
+	if (flushed >= CONFIG_CACHE_FLUSH_WATCHDOG_THRESHOLD) {
+		WATCHDOG_RESET();
+		flushed = 0;
+	}
+	return flushed;
+}
+
 void flush_cache(ulong start_addr, ulong size)
 {
 	ulong addr, start, end;
+	ulong flushed = 0;
 
 	start = start_addr & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
 	end = start_addr + size - 1;
@@ -19,7 +30,7 @@
 	for (addr = start; (addr <= end) && (addr >= start);
 			addr += CONFIG_SYS_CACHELINE_SIZE) {
 		asm volatile("dcbst 0,%0" : : "r" (addr) : "memory");
-		WATCHDOG_RESET();
+		flushed = maybe_watchdog_reset(flushed);
 	}
 	/* wait for all dcbst to complete on bus */
 	asm volatile("sync" : : : "memory");
@@ -27,7 +38,7 @@
 	for (addr = start; (addr <= end) && (addr >= start);
 			addr += CONFIG_SYS_CACHELINE_SIZE) {
 		asm volatile("icbi 0,%0" : : "r" (addr) : "memory");
-		WATCHDOG_RESET();
+		flushed = maybe_watchdog_reset(flushed);
 	}
 	asm volatile("sync" : : : "memory");
 	/* flush prefetch queue */